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<A name="Timing_rpt_top">Timing Report</A><B><U><big></big></U></B>
Lattice Timing Report -  Setup  and Hold, Version Radiant Software (64-bit) 2022.1.0.52.3

Sun Mar 12 05:42:37 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.

Command line:    timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp High-Performance_1.2V -hsp m -pwrprd -html -rpt dds_pro_impl_1.twr dds_pro_impl_1.udb -gui

-----------------------------------------
Design:          hs_dac
Family:          iCE40UP
Device:          iCE40UP5K
Package:         SG48
Performance:     High-Performance_1.2V
Package Status:                     Preliminary    Version 1.5
**Performance Hardware Data Status :   Advanced Version 1.0
-----------------------------------------


=====================================================================
                    Table of Contents
=====================================================================
<LI>    <A href=#Timing_rpt_DesignChecking>1  DESIGN CHECKING</A></LI>
<LI>        <A href=#Timing_rpt_SDCConstraints>1.1  SDC Constraints</A></LI>
<LI>        <A href=#Timing_rpt_ConstraintCoverage>1.2  Constraint Coverage</A></LI>
<LI>        <A href=#Timing_rpt_OverallSummary>1.3  Overall Summary</A></LI>
<LI>        <A href=#Timing_rpt_UnconstrainedReport>1.4  Unconstrained Report</A></LI>
<LI>        <A href=#Timing_rpt_CombinationalLoop>1.5  Combinational Loop</A></LI>
<LI>        <A href=#Timing_rpt_ErrorWarningMessage>1.6  Error/Warning Messages</A></LI>
<LI>    <A href=#Timing_rpt_SetupSlowCornerMaxDegree>2  Setup at Speed Grade High-Performance_1.2V Corner at 100 Degrees</A></LI>
<LI>        <A href=#Timing_rpt_ClockSummarySetupSlowCornerMaxDegree>2.1  Clock Summary</A></LI>
<LI>        <A href=#Timing_rpt_EndpointSlackSetupSlowCornerMaxDegree>2.2  Endpoint slacks</A></LI>
<LI>        <A href=#Timing_rpt_DetailReportSetupSlowCornerMaxDegree>2.3  Detailed Report</A></LI>
<LI>    <A href=#Timing_rpt_HoldFastCornerMinDegreeNoAV>3  Hold at Speed Grade m Corner at 100 Degrees</A></LI>
<LI>        <A href=#Timing_rpt_EndpointSlackHoldFastCornerMinDegreeNoAV>3.1  Endpoint slacks</A></LI>
<LI>        <A href=#Timing_rpt_DetailReportHoldFastCornerMinDegreeNoAV>3.2  Detailed Report</A></LI>

=====================================================================
                    End of Table of Contents
=====================================================================


<A name="Timing_rpt_DesignChecking"></A><B><U><big>1  DESIGN CHECKING</big></U></B>

<A name="Timing_rpt_SDCConstraints"></A><B><U><big>1.1  SDC Constraints</big></U></B>

[IGNORED:]create_generated_clock -name {clk_60M} -source [get_pins u_pll_60M.lscc_pll_inst.u_PLL_B/REFERENCECLK] -multiply_by 5 [get_pins u_pll_60M.lscc_pll_inst.u_PLL_B/OUTCORE]

<A name="Timing_rpt_ConstraintCoverage"></A><B><U><big>1.2  Constraint Coverage</big></U></B>

Constraint Coverage: 0%

<A name="Timing_rpt_OverallSummary"></A><B><U><big>1.3  Overall Summary</big></U></B>

 Setup at Speed Grade High-Performance_1.2V Corner at 100 Degrees     Timing Errors: 0 endpoints;  Total Negative Slack: 0.000 ns 
 Hold at Speed Grade m Corner at 100 Degrees                          Timing Errors: 0 endpoints;  Total Negative Slack: 0.000 ns 

<A name="Timing_rpt_UnconstrainedReport"></A><B><U><big>1.4  Unconstrained Report</big></U></B>

<A name="Timing_rpt_UnconstrainedEndpoints"></A><B><U><big>1.4.1  Unconstrained Start/End Points</big></U></B>

Clocked but unconstrained timing start points
--------------------------------------------------
There is no start point satisfying reporting criteria


Clocked but unconstrained timing end points
-------------------------------------------------------------------
         Listing 10 End Points          |           Type           
-------------------------------------------------------------------
u_da_wave_send/phase_acc_94__i32/D      |    No arrival or required
u_da_wave_send/phase_acc_94__i31/D      |    No arrival or required
{u_da_wave_send/phase_acc_94__i31/SP   u_da_wave_send/phase_acc_94__i32/SP}                           
                                        |    No arrival or required
{u_da_wave_send/phase_acc_94__i31/SR   u_da_wave_send/phase_acc_94__i32/SR}                           
                                        |    No arrival or required
u_da_wave_send/phase_acc_94__i30/D      |    No arrival or required
u_da_wave_send/phase_acc_94__i29/D      |    No arrival or required
{u_da_wave_send/phase_acc_94__i29/SP   u_da_wave_send/phase_acc_94__i30/SP}                           
                                        |    No arrival or required
{u_da_wave_send/phase_acc_94__i29/SR   u_da_wave_send/phase_acc_94__i30/SR}                           
                                        |    No arrival or required
u_da_wave_send/phase_acc_94__i28/D      |    No arrival or required
u_da_wave_send/phase_acc_94__i27/D      |    No arrival or required
-------------------------------------------------------------------
                                        |                          
Number of unconstrained timing end poin |                          
ts                                      |                       348
                                        |                          
-------------------------------------------------------------------

<A name="Timing_rpt_StartEndPointsWithoutTimingConstraints"></A><B><U><big>1.4.2  Start/End Points Without Timing Constraints</big></U></B>

I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...

-------------------------------------------------------------------
     Listing 10 Start or End Points     |           Type           
-------------------------------------------------------------------
clk_12M                                 |                     input
key_rst_n                               |                     input
SCK                                     |                     input
SSEL                                    |                     input
MOSI                                    |                     input
da_data[6]                              |                    output
da_data[7]                              |                    output
da_data[8]                              |                    output
da_data[9]                              |                    output
MISO                                    |                    output
-------------------------------------------------------------------
                                        |                          
Number of I/O ports without constraint  |                        17
                                        |                          
-------------------------------------------------------------------

Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
--------------------------------------------------
There is no instance satisfying reporting criteria



<A name="Timing_rpt_CombinationalLoop"></A><B><U><big>1.5  Combinational Loop</big></U></B>

None



<A name="Timing_rpt_ErrorWarningMessage"></A><B><U><big>1.6  Error/Warning Messages</big></U></B>

WARNING - No master clock for
	generated clock	create_generated_clock -name {clk_60M} -source [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/REFERENCECLK}] -multiply_by 5 [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/OUTCORE }] .

<A name="Timing_rpt_SetupSlowCornerMaxDegree"></A><B><U><big>2  Setup at Speed Grade High-Performance_1.2V Corner at 100 Degrees</big></U></B>
<A name="Timing_rpt_ClockSummarySetupSlowCornerMaxDegree"></A><B><U><big>2.1  Clock Summary</big></U></B>
<A name="Timing_rpt_Clk_1"></A><B><U><big>2.1.1 Clock "clk_60M"</big></U></B>

create_generated_clock -name {clk_60M} -source [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/REFERENCECLK}] -multiply_by 5 [get_pins {u_pll_60M/lscc_pll_inst/u_PLL_B/OUTCORE }] 

Single Clock Domain
-------------------------------------------------------------------------------------------------------
             Clock clk_60M              |                    |       Period       |     Frequency      
-------------------------------------------------------------------------------------------------------
 From clk_60M                           |             Target |               +INF |          0.000 MHz 
                                        | Actual (all paths) |           1.336 ns |        748.503 MHz 
u_tri_rom/lscc_rom_inst/u_rom/PRIM_MODE.xADDR[0].xDATA[2].mem_file.mem0/iCE40UP.sp4k/RCLK (MPW)                                                                
                                        |   (50% duty cycle) |           1.336 ns |        748.503 MHz 
-------------------------------------------------------------------------------------------------------

Clock Domain Crossing

<A name="Timing_rpt_EndpointSlackSetupSlowCornerMaxDegree"></A><B><U><big>2.2  Endpoint slacks</big></U></B>
--------------------------------------------------
There is no end point satisfying reporting criteria

Total Negative Slack: 0


<A name="Timing_rpt_DetailReportSetupSlowCornerMaxDegree"></A><B><U><big>2.3  Detailed Report</big></U></B>


XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Detail report of critical paths

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                    Detailed Report for timing paths 
 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                    End of Detailed Report for timing paths 
 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++


##########################################################



<A name="Timing_rpt_HoldFastCornerMinDegreeNoAV"></A><B><U><big>3  Hold at Speed Grade m Corner at 100 Degrees</big></U></B>
<A name="Timing_rpt_EndpointSlackHoldFastCornerMinDegreeNoAV"></A><B><U><big>3.1  Endpoint slacks</big></U></B>
--------------------------------------------------
There is no end point satisfying reporting criteria

Total Negative Slack: 0


<A name="Timing_rpt_DetailReportHoldFastCornerMinDegreeNoAV"></A><B><U><big>3.2  Detailed Report</big></U></B>


XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Detail report of critical paths

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                    Detailed Report for timing paths 
 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                    End of Detailed Report for timing paths 
 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++


##########################################################








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</PRE></DIV>

<DIV id="toc" class="radiant"<span onmousemove="showTocList()">Contents</span>
<UL id="toc_list">
<LI><A href=#Timing_rpt_top>Timing Report</A></LI>
<LI><A href=#Timing_rpt_DesignChecking>1  DESIGN CHECKING</A></LI>
<UL>
<LI><A href=#Timing_rpt_SDCConstraints>1.1  SDC Constraints</A></LI>
<LI><A href=#Timing_rpt_ConstraintCoverage>1.2  Constraint Coverage</A></LI>
<LI><A href=#Timing_rpt_OverallSummary>1.3  Overall Summary</A></LI>
<LI><A href=#Timing_rpt_UnconstrainedReport>1.4  Unconstrained Report</A></LI>
<LI><A href=#Timing_rpt_CombinationalLoop>1.5  Combinational Loop</A></LI>
<LI><A href=#Timing_rpt_ErrorWarningMessage>1.6  Error/Warning Messages</A></LI>
</UL>
<LI><A href=#Timing_rpt_SetupSlowCornerMaxDegree>2  Setup at User Specified Speed Grade Corner at User Specified Degrees</A></LI>
<UL>
<LI><A href=#Timing_rpt_ClockSummarySetupSlowCornerMaxDegree>2.1  Clock Summary</A></LI>
<LI><A href=#Timing_rpt_EndpointSlackSetupSlowCornerMaxDegree>2.2  Endpoint slacks</A></LI>
<LI><A href=#Timing_rpt_DetailReportSetupSlowCornerMaxDegree>2.3  Detailed Report</A></LI>
</UL>
<LI><A href=#Timing_rpt_HoldFastCornerMinDegreeNoAV>3  Hold at User Specified Speed Grade Corner at User Specified Degrees</A></LI>
<UL>
<LI><A href=#Timing_rpt_EndpointSlackHoldFastCornerMinDegreeNoAV>3.1  Endpoint slacks</A></LI>
<LI><A href=#Timing_rpt_DetailReportHoldFastCornerMinDegreeNoAV>3.2  Detailed Report</A></LI>
</UL>
</UL>
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